Chip packaging is no longer limited to providing protection and I/O expansion interfaces for independent chips in the traditional sense. Today, more and more packaging technologies can realize the interconnection between different chips. Advanced packaging processes can increase device density and thus reduce space requirements, which is critical for functional stacking in electronic devices such as mobile phones and self-driving cars. The development of the chip packaging industry has made the International Institute of Electrical and Electronic Engineers (IEEE-CPMT) realize that it must expand its technical scope, and officially changed its name to the International Institute of Electrical and Electronics Engineers Electronics Packaging Institute (IEEE-CPMT) in 2017. – EPS).
There is an advanced packaging technology called “wafer-level packaging” (WLP), which is the packaging of integrated circuits directly on the wafer. Packaging through this process can produce wafers that are nearly the same size as the original die. Embedded Wafer Level Ball Grid Array (eWLB) developed by Infineon in the late 2000s is a wafer level packaging technology. There are a number of packaging and testing foundries (OSATs) currently using a variant of eWLB. Specifically, eWLB packaging refers to placing the qualified wafer face down on the carrier wafer and embedding the two as a whole into an epoxy mold. “Fan-out” packaging followed by die-casting reconstituted wafer structures, redistribution layer processes (RDLs) and ball placement on the exposed wafer surface, which are then diced to obtain ready-to-use chips (figure 1).
Through silicon via technology (TSV) refers to vertical interconnects that completely penetrate the silicon substrate. Figure 2 shows the TSV technology based on silicon interposer, that is, the electrical connection between the high-density die and the packaging layer is achieved through the silicon interposer. The technology was initially popularized as an alternative to wire bonding, enabling 3D integration through multiple die stacks while reducing interconnect length to optimize resistance.
As an application of conductive interconnect technology, the role of the redistribution layer is to redistribute the electronic circuits connected to the die pad I/O points, and can be placed on one or both sides of a single die. As the demand for bandwidth and I/O points increases, the line width and spacing of the redistribution layer also need to be continuously reduced. In order to meet these requirements, the copper damascene technology similar to the back-end process has been adopted in the current process to reduce the line width, and the distance between the chips is reduced by replacing the traditional solder bumps with copper pillars.
Advanced packaging technologies continue to evolve to meet ever-increasing device density and I/O connectivity performance requirements. The copper hybrid bonding technology that has emerged in recent years is a good example. Its role is to directly connect copper bumps and dielectrics on one surface to the corresponding area on the other active surface, thereby circumventing the limitation of bump pitch. We are very much looking forward to these innovations in packaging technology to lead the steady development of a new generation of electronic products.